Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!ittatc!dcdwest!sdcsvax!drillsys!gatech!seismo!ut-sally!utastro!nather From: nather@utastro.UUCP (Ed Nather) Newsgroups: net.arch Subject: Re: The PDP-8 -- the first RISC architecture Message-ID: <474@utastro.UUCP> Date: Thu, 6-Mar-86 14:46:38 EST Article-I.D.: utastro.474 Posted: Thu Mar 6 14:46:38 1986 Date-Received: Sun, 9-Mar-86 08:25:51 EST References: <187@anwar.UUCP> <1441@gitpyr.UUCP> <890@umn-cs.UUCP> <143@ima.UUCP> Organization: U. Texas, Astronomy, Austin, TX Lines: 82 Keywords: RISC PDP-8 ancient_history In article <143@ima.UUCP>, johnl@ima.UUCP (John R. Levine) writes: > The PDP-5, the architecturally compatible predecessor of the PDP-8, was by any > definition the first RISC design. [ ... ] They were also > familiar with the Lincoln Labs LINC, a 12 bit machine designed for laboratory > use, and the machine that brought us DECtape -- a cheap block addressable > medium which was in a sense a very floppy disk conveniently wound on a spool. ...which was, by any definition, the first RISC computer, since it had the same instruction set as the later DEC machines. It was designed at Lincoln Labs by Wesley A. Clark, inventor of the first Average Response Computer, and of the phrases "self-organizing systems" and "intelligent terminals" among many others. He got DEC to produce the boards for his Laboratory Instrument Computer (LINC) which users themselves were to assemble, to save cost. It had a whopping 1K words of memory (12 bits each) and had autoindexing registers in memory, mostly because Clark ran out of bits in the instruction word, and had to leave out the "uppit bit" which was to auto-increment addresses to effect indexing operations. > The PDP-8 had an instruction set pared down to a minimum. > > Op code mnemonic use > 0 AND logical and accumulator with memory > 1 TAD add memory to accumulator (T for twos-complement) > 2 ISZ increment accumulator, skip next instr if zero I'm pretty sure this incremented a memory address, not the accumulator. > 3 DCA deposit accumulator in memory, clear accumulator > 4 JMS jump to subroutine and store return address > 5 JMP jump > 6 IOT various I/O instructions > 7 OPR various accumulator operations and tests > > An interesting side note is that the logic design of the 5 was done by Ed > DeCastro. He later had a sixteen bit design that DEC rejected in favor of I believe he left DEC first, founded Data General, did well, and goaded DEC into coming out with the PDP-11 as an answer to the Nova. DEC, I'm told, rejected the 16-bit design because it was not instruction-compatible with the PDP-8. DeCastro made the same blunder by demanding that the Eclipse et. seq. be backward-compatible with the Novae, so the original, clean instruction set design is now a pile of garbage. The nova arithmetic system consists entirely of combinations of three basic operations in triple-sequence: negate, add, and increment: neg add incr Operation 0 0 0 NOP 0 0 1 INCrement 0 1 0 ADD 0 1 1 AND (preempted because add, incr not useful) 1 0 0 NEGate 1 0 1 COMplement 1 1 0 ADC (add complement) 1 1 1 SUBtract In actual implementation, the coding for the negate operation was inverted but the logic is unchanged. I find this elegant -- and RISCy. This set of operations is just one step of the five (5) sequential operations available in a SINGLE INSTRUCTION on the Nova computers. (The others allow the carry bit to be pre-set, the result of the operation shifted left or right 1 bit, the result tested (skip next instruction if ...) and, finally, the operation's result re-loaded into the target register or discarded. While I can see the problem compiler-writers have with a system like this, a careful assembly-larguage programmer can write fast, short code for some surprisingly complicated operations. In the infamous "sieve" benchmark the operation I + I + 3 in the inner loop can be done in a single Nova instruction. "What do you mean? These *are* the Good Old Days!" -- Ed Nather Astronomy Dept, U of Texas @ Austin {allegra,ihnp4}!{noao,ut-sally}!utastro!nather nather@astro.UTEXAS.EDU