Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!whuxl!whuxlm!akgua!gatech!seismo!mcvax!boring!jack
From: jack@boring.UUCP
Newsgroups: net.arch
Subject: Separate I/D caches. (was: Re: risc  questions)
Message-ID: <6813@boring.UUCP>
Date: Thu, 6-Mar-86 20:41:04 EST
Article-I.D.: boring.6813
Posted: Thu Mar  6 20:41:04 1986
Date-Received: Sun, 9-Mar-86 08:36:53 EST
References: <1511@decwrl.DEC.COM>
Reply-To: jack@mcvax.UUCP (Jack Jansen)
Distribution: net.arch
Organization: AMOEBA project, CWI, Amsterdam
Lines: 11
Keywords: Risc,cache,performance
Apparently-To: rnews@mcvax

In my opinion, two caches, one for instruction, one for data,
should perform almost as good as a two-way cache. The big
advantage seems to be that it's almost as easy to construct
as a one-way cache, provided the CPU gives an indication of
which cycles are I and which are D.

But, who am I to ramble away on this.... Anyone got some real
research results?
-- 
	Jack Jansen, jack@mcvax.UUCP
	The shell is my oyster.