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From: david@ztivax.UUCP
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <2900002@ztivax.UUCP>
Date: Thu, 6-Mar-86 14:44:00 EST
Article-I.D.: ztivax.2900002
Posted: Thu Mar  6 14:44:00 1986
Date-Received: Sun, 9-Mar-86 08:37:39 EST
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Nf-From: ztivax!david    Mar  6 19:44:00 1986

/* Written  4:27 pm  Feb 24, 1986 by jer@peora in ztivax:net.arch */
>> As far as I'm concerned, the test for RISCness should be: given any piece
>> of source code, is there only one reasonable code sequence which can be
>> output by the compiler?

>How is that a test for "RISCness"?  Following the above scheme, you could,
>for example, have a machine that directly (and optimally) interpreted some
>concise representation of the source code... but that's exactly what people
>are calling a CISC machine, and are claiming is bad...

Sorry jer, but those CISC machines have some super instructions which are
of LIMITED SCOPE, and therefore CANNOT be directly and optimally
substituted for the source code.  Instead you must perform many complicated
what if?s before deciding if you can use the instruction more easily than
the low level instructions which can ALWAYS be used.

For example, lets say you were going to do ANYTHING with an intel (aka
Brain Damage (*$Q##!)) 80*8*.  Look thru the book, you'll find some super
instruction.  Only problem is, how many registers must you store (and
where?) to set up for it, and how many do you need to restore?  Sometimes
(if you just happened to have only garbage in the registers), it IS optimal
to do character translations with that XLT (or is it TLX, or #%&*%?).
Often (typically) it is not.

The thing is:  Its got the fancy instructions, and the simple instructions,
and SOMETIMES the fancy ones fit the specific high level functions, and
SOMETIMES they dont.

And that is a pain in the ass.

david smyth
free and proud of it

seismo!unido!ztivax!david