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From: david@ztivax.UUCP
Newsgroups: net.arch
Subject: Re: RISC vs INTEL
Message-ID: <2900006@ztivax.UUCP>
Date: Thu, 6-Mar-86 15:57:00 EST
Article-I.D.: ztivax.2900006
Posted: Thu Mar  6 15:57:00 1986
Date-Received: Sun, 9-Mar-86 08:38:30 EST
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Nf-From: ztivax!david    Mar  6 20:57:00 1986

> hammond@petrus writes:
> sun!pyramid!dan writes:
>> ...  Yes, there are
>> RISC machines that have some multiple cycle instructions.  In my experience,
>> though, something like a block move can usually be implemented with a loop
>> (especially using an efficient branch scheme) of simpler instructions with
>> *no loss of performance*.
> 
>*NO LOSS OF PERFORMANCE?!?  No way!  Look, a memory block move is a RISC
>at its worst, since the block move defeats the data cache.  A M68000 
>(16 bit data and instruction bus) is FASTER than the UCB RISC (32 bit
>data and instruction bus) for equivalent 32 bit at a time block moves.
>Even if the RISC instructions are in a cache, the data isn't and what's
>worse, every other data access is a write.  Essentially, the block transfer
>measures data bus bandwidth, not cache bandwidth, which is what RISCs
>exploit.

OK, so here we have a classic example of how a CISC instruction does
not help.  A CISC microcodes the action on-chip.  A RISC uses on-chip
cache.  Both are speed limited by the memory access times.  That is
possibly why the 68000 can do this as fast as the RISC - were the 
memory access times were similar?

So here, RISC at its worst, the same as CISC at its best?

David Smyth
Free and proud of it

seismo!unido!ztivax!david