Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.1 6/24/83; site ubc-cs.UUCP
Path: utzoo!utcsri!ubc-vision!ubc-cs!ludemann
From: ludemann@ubc-cs.UUCP (Peter Ludemann)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <185@ubc-cs.UUCP>
Date: Sun, 9-Mar-86 20:43:27 EST
Article-I.D.: ubc-cs.185
Posted: Sun Mar  9 20:43:27 1986
Date-Received: Sun, 9-Mar-86 21:43:04 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1433@gitpyr.UUCP> <169@ubc-cs.UUCP> <1163@mmintl.UUCP>
Reply-To: ludemann@ubc-cs.UUCP (Peter Ludemann)
Organization: UBC Department of Computer Science, Vancouver, B.C., Canada
Lines: 35
Keywords: RISC, optimiser, compiler

In article <1163@mmintl.UUCP> franka@mmintl.UUCP (Frank Adams) writes:
>In article <169@ubc-cs.UUCP> ludemann@ubc-cs.UUCP (Peter Ludemann) writes:
>>As far as I'm concerned, the test for RISCness should be: given any
>>piece of source code, is there only one reasonable code sequence which can be
>>output by the compiler?
>
>This is not a possible objective.  Consider sequences like:
>
>   A = B[I];
>   C = D[I];
>
>On any machine which has registers, it is possible ...
>	(description of optimisations possible)

You miss my point.  The optimisations described (in this case common 
expression detection) are possible *regardless* of the target 
machine's architecture.  Any good compiler should try to optimise 
code like this.  However, once these "source level" and flow analysis 
optimisations are finished, there should be only one reasonable way 
of generating the machine code.  Otherwise, the poor compiler writer 
has to do another set of optimisation analyses, all because of the 
target machine's instruction set.  

As an aside, the MVCL (move character long) instruction on the 
IBM/370 machines was actually slower than an equivalent loop which 
used a simple block move instruction.  Although later models improved 
the situation, it is interesting to note that IBM's "optimizing" PL/1 
compiler still generates a subroutine which does *exactly* what a 
MVCL instruction does (even with the same register usage 
conventions).  
-- 
-- Peter Ludemann
	ludemann@ubc-cs.uucp (ubc-vision!ubc-cs!ludemann)
	ludemann@cs.ubc.cdn  (ludemann@cs.ubc.cdn@ubc.mailnet)
	ludemann@ubc.csnet   (ludemann%ubc.csnet@CSNET-RELAY.ARPA)