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From: john@ektools.UUCP
Newsgroups: net.arch
Subject: Re: RISC question
Message-ID: <377@ektools.UUCP>
Date: Fri, 7-Mar-86 11:17:00 EST
Article-I.D.: ektools.377
Posted: Fri Mar  7 11:17:00 1986
Date-Received: Mon, 10-Mar-86 00:18:15 EST
References: <1181@ecsvax.UUCP> <411@ccivax.UUCP> <375@ektools.UUCP> <738@ihwpt.UUCP> <449@ccivax.UUCP>
Reply-To: john@ektools.UUCP (John H. Hall)
Distribution: net
Organization: Eastman Kodak, Dept. 47
Lines: 43

In article <449@ccivax.UUCP> rb@ccivax.UUCP (What's in a name ?) writes:
>Yup!  If you ran ALL instructions directly from main memory, this would
>be correct, but RISC chips usually have either internal or tightly
>coupled CACHE which reduces the number of fetches from main RAM.  In
>fact, some RISC machines have several LAYERS of CACHE, such as 2K
>internal, 2 meg external, then the bus, and even a cache to the disk.

Is there some reason that RISC machines require cache to operate? 

Are the benefits of cache greater for RISC architectures?

I guess I see cache as an architectural feature separate from the
RISC-iness of a machine's instructions set.

Indeed, many modern computers incorporate both RISC instruction sets and
cache memories.  Is this cause and effect, or are these merely two
good ideas that are being used in the same machine?

Why wouldn't cache benefit a CISC machine?

For single-chip designs, given a particular die-size and line width it
is easier to find room for on-chip cacheing with a RISC design.  (Of
course, the extra space could also be used for a huge register file,
another "RISC characteristic" that seems to be equally applicable to
CISC designs.). 

Are we muddying the waters by lumping a bunch of good ideas:
   - Reduced instruction sets
   - Large register files
   - Multi-layer cache
all into the category of RISC?


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John Hall
Supervisor, Software Tools Laboratory
Product Software Engineering

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