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From: reiter@harvard.UUCP (Ehud Reiter)
Newsgroups: net.arch
Subject: Re: RISC cache vs CISC u-code
Message-ID: <765@harvard.UUCP>
Date: Sat, 8-Mar-86 12:17:30 EST
Article-I.D.: harvard.765
Posted: Sat Mar  8 12:17:30 1986
Date-Received: Tue, 11-Mar-86 01:42:50 EST
References: <136@pyramid.UUCP> <570@imag.UUCP> <4521@think.ARPA>
Reply-To: reiter@harvard.UUCP (Ehud reiter)
Organization: Aiken Comp Lab, Harvard
Lines: 36
Summary: No cache on an RT and other RT notes

The numerous articles on RISC machines have all assumed that such machines have
caches.  However, the only commercial RISC machine that I'm familiar with, the
IBM PC/RT, does NOT have a cache, and seems to suffer a factor of 3 performance
degradation because of this (2 MIPS instead of 6 MIPS).  To quote from IBM RT
PERSONAL COMPUTER TECHNOLOGY  (probably available from your friendly
neighborhood IBM salesman), pg 48 - "The 801 minicomputer ... had exceptionally
high performance.  However, much of its performance depended on its two caches,
which can deliver an instruction word and a data word on each CPU cycle.  SINCE
SUCH CACHES WERE PROHIBITIVELY COSTLY FOR SMALL SYSTEMS ..." (emphasis mine).

The point is that you can't assume that RISC machines have caches, because some
don't.  And, as near as I can tell, an RT has much less performance than a
SUN 3 (lousy floating point and I/O as well as no cache), but costs twice as
much ($15k vs $8k for diskless systems (??) ).  So, if RISC machines need
caches to perform well, then CISC machines win out, at least at the bottom end
of the market.

Incidentally, the RT has an "overlapped load" feature, where instructions that
don't reference the loaded data can be executed concurrently with a LOAD
instruction.  The only problem is, this feature is disabled in virtual memory
mode (presumably because of the difficulty of saving the state of the machine
when a page fault occurs).  A case of the "cruel real world" destroying a
cute RISC idea?

One last point - the RT does NOT have a fancy subroutine call mechanism (like
Berkeley's RISC).  So, even if it were true that an RT could execute a MULTIPLY
routine out of memory as fast as a CISC machine could execute it out of
microcode, the RISC multiply is much more expensive because of the subroutine
call overhead.

I highly recommend reading IBM RT PERSONAL COMPUTER TECHNOLOGY - its very well
written, and it shows you what the pros and cons of a real machine.

						Ehud Reiter
						harvard!reiter.UUCP
						reiter@harvard.ARPA