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From: hammond@petrus.UUCP (Rich A. Hammond)
Newsgroups: net.arch
Subject: Re: RISC vs INTEL
Message-ID: <43@petrus.UUCP>
Date: Mon, 10-Mar-86 07:40:03 EST
Article-I.D.: petrus.43
Posted: Mon Mar 10 07:40:03 1986
Date-Received: Wed, 12-Mar-86 01:39:06 EST
References: <117@pyramid.UUCP> <2900006@ztivax.UUCP>
Organization: Bell Communications Research, Inc
Lines: 21

I pointed out that a 68000 could do block moves of 32 bit words FASTER
than the UCB RISC I or II for equivalent memory access times.
> David Smyth responded:
> 
> OK, so here we have a classic example of how a CISC instruction does
> not help.  A CISC microcodes the action on-chip.  A RISC uses on-chip
> cache.  Both are speed limited by the memory access times.  That is
> possibly why the 68000 can do this as fast as the RISC - were the 
> memory access times were similar?
> 
> So here, RISC at its worst, the same as CISC at its best?

NO WAY, as I pointed out, the 68000 has 16 bit data bus (i.e. 2 memory
cycles for each read and write of 32 bit words) while the RISC I & II
have a 32 bit data bus.  IF the CISC 68000 had the same size data bus
it would save 2 memory cycles, out of a total of 7 or be about 30%
faster than the RISC.  Of course this benchmark is never included for
RISC vs CISC comparisons.  However, copy loops occur much more frequently
in real code than benchmarks such as Ackermann's function.

Rich Hammond