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From: jeffj@sfmin.UUCP (J.S.Jonas)
Newsgroups: net.arch
Subject: address != data != instruction length
Message-ID: <670@sfmin.UUCP>
Date: Mon, 10-Mar-86 18:18:00 EST
Article-I.D.: sfmin.670
Posted: Mon Mar 10 18:18:00 1986
Date-Received: Wed, 12-Mar-86 03:03:57 EST
Distribution: net
Organization: AT&T Bell Laboratories, Summit N.J.
Lines: 46

From postnews Fri Feb 28 18:09:19 1986
Subject: Re: RISC question
Newsgroups: net.arch
References: <2809@gatech.CSNET> <9921@amdcad.UUCP>

> In article <2809@gatech.CSNET>, dana@gatech.CSNET (Dana Eckart) writes:
> > I can not think of a "good" reason why 24 bit architectures are not
> > used instead.
> >                        Have we surrendered to 32 bits without a "good"
> > reason?
> 
> The reason that 32-bit architectures are so popular is addressing
> range:  a 32-bit address space is nice and big (for now at least)
> but a 24-bit address space is too small.  Since the CPU has to

	Why do you equate address length with data length with
instruction length?  I know that addresses are handled as data, so if
the address length = data length, then registers can hold an
entire address (unlike the 8088/6 with 16 bit registers and 20 bit address).
[okay, the address can be any length after the MMU is through with it
since the CPU has no access to the bus address].

	I think that the instruction length can be different.  A dedicated
systems using ROM code could have a 13 bit instruction length and
32 bit address/data length.  The instruction data path could be
separate from the data path (instruction in 13 bit wide ROM,
data in 32 bit wide RAM), or the data lines could be used (just
ignore the upper bits).  Yes, there will be two memory systems,
but if you're running separate I/D space that's not news to you.

	Now say you want a system with loadable programs.  Will you
need a 13 bit-word disk for programs and a 32 bit word disk for data?
No, you could put the instructions in the data space either unpacked
or packed.  How about this - the instructions are packed in data
memory (you could put 2 instructions per word with 7 bits wasted,
or try to span words (yeccch)).  The instructions are read into
cache where they are unpacked as needed.  Reading 2 instructions
per cycle seems attractive to me.  This then eliminates the need
for two memory systems.

	I recall that a single bit processor (I don't remember the
number) had a 4 bit instruction but 1 bit data/registers (flags really),
so instruction size != data size.  The PC was external to the chip.

				Jeff 'just thought of it' Skot
				{ihnp4 | allegra | cbosgd} attunix ! jeffj