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From: holmer@ji.berkeley.edu (Bruce K. Holmer)
Newsgroups: net.arch
Subject: Re: risc  questions
Message-ID: <12292@ucbvax.BERKELEY.EDU>
Date: Sun, 9-Mar-86 18:06:38 EST
Article-I.D.: ucbvax.12292
Posted: Sun Mar  9 18:06:38 1986
Date-Received: Wed, 12-Mar-86 03:34:09 EST
References: <1511@decwrl.DEC.COM> <5100023@ccvaxa>
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Reply-To: holmer@ji.berkeley.edu.UUCP (Bruce K. Holmer)
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In article <5100023@ccvaxa> aglew@ccvaxa.UUCP writes:
>
>> /* Written 10:40 pm  Mar  4, 1986 by paulr@decwrl.DEC.COM */
>> Has anyone taken data as to the performance gains/losses attributed
>> to separate data/instruction caches in processors.You can reply to me
>> at the above address,or to the net,but i am interested in info
>> 
>> 						Paul Richardson
>
>I'd be interested in the results. 

If you haven't already done so, be sure to take a look at the article:
	Smith, A.J., "Cache Memories," Computing Surveys 14, 3 
	(Sept. 1982) pp. 473-530.
Section 2.8 of this paper gives trace-driven simulations for separate
data/instruction caches.  Also, several machines are mentioned (S-1,
801, Hitachi H200, and Itel AS/6), but no measurements were available at
the time the article was written.