Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site decwrl.DEC.COM
Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!decwrl!paulr
From: paulr@decwrl.DEC.COM (Paul Richardson)
Newsgroups: net.arch
Subject: Re: Addressing modes ("High Level" instructions)
Message-ID: <1593@decwrl.DEC.COM>
Date: Sun, 9-Mar-86 23:16:06 EST
Article-I.D.: decwrl.1593
Posted: Sun Mar  9 23:16:06 1986
Date-Received: Wed, 12-Mar-86 21:56:23 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1476@lanl.ARPA> <78@cad.UUCP> <90@sbcs.UUCP>
Reply-To: paulr@decwrl.UUCP (Paul Richardson)
Organization: Digital Equipment Corporation
Lines: 28
Keywords: Vax 780
Summary: error

In article <90@sbcs.UUCP> debray@sbcs.UUCP (Saumya Debray) writes:
>Some time back, when working on a Prolog machine emulator on a Vax 780, we
>found that it was _significantly less efficient_ to use a single
>"Test, Set and Branch" instruction than it was to use three separate
>instructions to test, set and branch respectively.  This seemed very
>counterintuitive until we realized that instructions with 2 operands or
>fewer had the operands decoded in hardware, while instructions with more
>than 2 operands (e.g the "test-set-branch" instruction) had to go to
>microcode for this.  I guess the extra instruction fetches for the case
>using three separate instructions overlapped sufficiently due to pipelining
>to give the hardware decoding an overwhelming edge.
>

>Saumya Debray
>SUNY at Stony Brook
>
>	uucp: {allegra, hocsd, philabs, ogcvax} !sbcs!debray
>	arpa: debray%suny-sb.csnet@csnet-relay.arpa
>	CSNet: debray@sbcs.csnet


While I cannot profess knowledge about the Vax 11/780 microcode,I do
believe that the 780 is NOT pipelined.I stand to be corrected,but i am 
fairly sure that the 8600 was/is the first pipelined implementation 
of the Vax architecture.

P.S-I could be wrong on the above,even Dec employees don't always know
what is going on