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From: dalel@athena.UUCP (Dale Lehmann)
Newsgroups: net.arch
Subject: Re: Re: Addressing modes
Message-ID: <31@athena.UUCP>
Date: Sun, 9-Mar-86 20:09:25 EST
Article-I.D.: athena.31
Posted: Sun Mar  9 20:09:25 1986
Date-Received: Wed, 12-Mar-86 22:08:07 EST
References: <187@anwar.UUCP> <1441@gitpyr.UUCP> <400@utastro.UUCP> <222@uvacs.UUCP> <1441@wucec2.UUCP>
Reply-To: dalel@athena.UUCP (Dale Lehmann)
Followup-To: net.arch
Distribution: net
Organization: Tektronix, Beaverton OR
Lines: 30
Keywords: RISC PDP-8
Summary: Memories...

------------
In article <1441@wucec2.UUCP> jdz@wucec2.UUCP (Jason D. Zions) writes:
>>
>> The TRUE RISC would have only one instruction: subtract....
>
>Not quite. You need two address, you see. If we go to two instructions, we
>can get away with only one address. To wit:
>
>	SUBS X	Subtract cotents of location X from accumulator and
>		store results in accumulator and in X
>
>	JUMP X	Indirect jump; i.e. PC <= contents of location X
>
>Proving this beast to be functionally complete is arduous but do-able.
>We use it as an exercise in our Computer Architecture class....

When I was working as a lab instructor for a computer class at
Oregon State University, two of the students in the class did
something similar to this.  They had run across the claim that
the minimum number of instructions a computer needed were
"subtract one" and "branch on negative".  They proceeded to
write a simulator for the PDP-8 instruction set using only two
instructions: ISZ (increment memory, skip if result is zero)
and JMP.  Talk about your extra-credit projects!

--
Dale Lehmann
Tektronix, Inc.
UUCP: ...!tektronix!teklds!dalel
USMail: P.O. Box 4600, Beaverton, Oregon  97075