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From: reiter@harvard.UUCP (Ehud Reiter)
Newsgroups: net.arch
Subject: Re: RISC cache vs CISC u-code
Message-ID: <769@harvard.UUCP>
Date: Tue, 11-Mar-86 10:15:08 EST
Article-I.D.: harvard.769
Posted: Tue Mar 11 10:15:08 1986
Date-Received: Fri, 14-Mar-86 04:20:39 EST
References: <136@pyramid.UUCP> <570@imag.UUCP> <4521@think.ARPA> <765@harvard.UUCP> <148@ima.UUCP>
Reply-To: reiter@harvard.UUCP (Ehud reiter)
Organization: Aiken Comp Lab, Harvard
Lines: 16
Summary: Bottom Line on RT

It's true that the IBM PC/RT, through a combination of instruction prefetch
and interleaved memory, does not wait for instruction fetches when executing
a sequential instruction stream.  However, other memory references are quite
expensive.  The "bottom line" is (quoting from page 49 of the RT book)

"Although most ROMP [RT] instructions execute in only one cycle, additional
cycles are taken when it is necessary to wait for data to be returned from
memory for Loads and Branches.  As a result, the ROMP takes about three cycles
on the average for each instruction"

In short, a cacheless RISC machine does not come anywhere close to the one
instruction per cycle goal.

						Ehud Reiter
						harvard!reiter.UUCP
						reiter@harvard.ARPA