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From: jlg@lanl.UUCP
Newsgroups: net.arch
Subject: Re: RISC cache vs CISC u-code
Message-ID: <278@lanl.ARPA>
Date: Mon, 10-Mar-86 14:43:07 EST
Article-I.D.: lanl.278
Posted: Mon Mar 10 14:43:07 1986
Date-Received: Fri, 14-Mar-86 06:15:28 EST
References: <136@pyramid.UUCP> <570@imag.UUCP> <4521@think.ARPA> <765@harvard.UUCP> <146@ima.UUCP>
Reply-To: jlg@a.UUCP (Jim Giles)
Organization: Los Alamos National Laboratory
Lines: 19

In article <765@harvard.UUCP> reiter@harvard.UUCP (Ehud reiter) writes:
>One last point - the RT does NOT have a fancy subroutine call mechanism (like
>Berkeley's RISC).  So, even if it were true that an RT could execute a MULTIPLY
>routine out of memory as fast as a CISC machine could execute it out of
>microcode, the RISC multiply is much more expensive because of the subroutine
>call overhead.

The 'RISC' machine I use doesn't call any subroutine to do multiplies.  The
CRAY implements ADD, SUBTRACT, and MULTIPLY for both integers and floats
and DIVIDE for floats only in the hardware with hardwired logic.  It's
expensive in hardware (lots of chips), but not nearly as expensive as CISC
microcoding would make it because of slow operation.  The whole idea of
RISC is to pick those instructions which are important for the application
for which the machine is used, and make them FAST!  So, don't assume that
certain instructions will not be found in RISC machines - depends on the
target market for the device.

J. Giles
Los Alamos