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From: aglew@ccvaxa.UUCP
Newsgroups: net.arch
Subject: Re: RISC cache vs CISC u-code
Message-ID: <5100027@ccvaxa>
Date: Wed, 12-Mar-86 21:53:00 EST
Article-I.D.: ccvaxa.5100027
Posted: Wed Mar 12 21:53:00 1986
Date-Received: Sat, 15-Mar-86 03:29:55 EST
References: <136@pyramid.UUCP>
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Nf-ID: #R:pyramid.UUCP:136:ccvaxa:5100027:000:484
Nf-From: ccvaxa.UUCP!aglew    Mar 12 20:53:00 1986


RISCs => caches => cache flushes => inefficiencies in multiprogramming.

In addition to being able to neglect cache flushes if the interval between 
context switches is long enough (in terms of instructions processed), context
switches will hopefully become less important on multi-microprocessor
machines, where you can schedule more processes per second for the entire
machine (an important number for real-time systems) but each processor will
be handling fewer context switches.