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From: aglew@ccvaxa.UUCP
Newsgroups: net.arch
Subject: Re: risc  questions
Message-ID: <5100028@ccvaxa>
Date: Wed, 12-Mar-86 22:12:00 EST
Article-I.D.: ccvaxa.5100028
Posted: Wed Mar 12 22:12:00 1986
Date-Received: Sat, 15-Mar-86 03:30:27 EST
References: <1511@decwrl.DEC.COM>
Lines: 15
Nf-ID: #R:decwrl.DEC.COM:1511:ccvaxa:5100028:000:801
Nf-From: ccvaxa.UUCP!aglew    Mar 12 21:12:00 1986


Separate instruction/data caches can perform much better than "two-way" 
caches. (1) because different algorithms can be used in each cache,
to take into account the different behaviour of instructions and data
(eg. keep loop heads and return points in the cache longer);
but the big win is (2) you can fetch both instruction and data (for the
previous instruction) simultaneously. This way all you have to do is
provide two ports on your CPU and cache chips, which is expensive, but 
possible. You don't have to dual-port all your memory chips. If you can
squeeze both caches onto the CPU chip, you only have to have one off-chip
memory port. By this simple fiat, you can almost double throughput.

Andy "Krazy" Glew. Gould CSD-Urbana. 
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