Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!linus!philabs!cmcl2!harvard!seismo!mcvax!unido!ztivax!david From: david@ztivax.UUCP Newsgroups: net.arch Subject: Re: What is MIL-STD-1750A? Message-ID: <2900007@ztivax.UUCP> Date: Tue, 11-Mar-86 09:57:00 EST Article-I.D.: ztivax.2900007 Posted: Tue Mar 11 09:57:00 1986 Date-Received: Sun, 16-Mar-86 10:43:35 EST References: <1080@terak.UUCP> Sender: notes@unido.UUCP Lines: 15 Nf-ID: #R:terak:-108000:ztivax:2900007:000:569 Nf-From: ztivax!david Mar 11 14:57:00 1986 1750 is a 16-bit processor architecture standard. The fairchild chip is one of the implementations, touted to be very good. It is a large (CISCy) instruction set, but still a nice one. It is nice because it is regular and orthogonal. Virtually every register (16?) can be used for virtually any instruction. As I remember (it has been 7 years now), there is not even a dedicated stack pointer, and call/return needs to say which register to use as sp. It is easy to program in assy and the compilers for it are efficient. Very 68Kish. seismo!unido!ztivax!david