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From: gnu@hoptoad.uucp (John Gilmore)
Newsgroups: net.arch
Subject: Re: Timing loops (H/W vs. S/W design)
Message-ID: <616@hoptoad.uucp>
Date: Sat, 15-Mar-86 23:50:50 EST
Article-I.D.: hoptoad.616
Posted: Sat Mar 15 23:50:50 1986
Date-Received: Mon, 17-Mar-86 03:49:51 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp> <613@sauron.UUCP> <25@cbm.UUCP>
Organization: Nebula Consultants in San Francisco
Lines: 12

In article <25@cbm.UUCP>, grr@cbm.UUCP (George Robbins) writes:
> Speaking of moot problems, the recovery time specification for the Z8530 is
> a non-problem in most applications.  The data sheet basically specifies that
> so many PCLK cycles must elapse between accesses.  Unless you are using an
> unusually slow PCLK, the overhead of the C style inb()/outb() subroutine calls
> will eat up the requisite cycles.  Assembly code may need a nop or two to
> guarentee cycles.

This is only true if you have an unusually slow CPU.  Ours overruns the
chip without trouble.  Maybe Commodore's doesn't.
-- 
John Gilmore  {sun,ptsfa,lll-crg,ihnp4}!hoptoad!gnu   jgilmore@lll-crg.arpa