Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!watmath!clyde!cbosgd!gatech!seismo!harvard!reiter From: reiter@harvard.UUCP (Ehud Reiter) Newsgroups: net.arch Subject: Re: RISC cache vs CISC u-code Message-ID: <777@harvard.UUCP> Date: Sat, 15-Mar-86 12:44:17 EST Article-I.D.: harvard.777 Posted: Sat Mar 15 12:44:17 1986 Date-Received: Mon, 17-Mar-86 04:17:25 EST References: <136@pyramid.UUCP> <570@imag.UUCP> <4521@think.ARPA> <765@harvard.UUCP> <6491@utzoo.UUCP> Reply-To: reiter@harvard.UUCP (Ehud reiter) Organization: Aiken Comp Lab, Harvard Lines: 61 Summary: A few figures I thought it would be nice to try to get some numbers to quantify RISC and CISC performance. The numbers below are hopefully not too full of bugs - I would be glad to send interested people references. 1) Cache, RISC, and MIPS - some figures for a VAX-11/780 cycles/inst MIPS cache disabled 25 .2 VAX's were not designed for this normal cache 10 .5 perfect cache 7 .7 MIPS rating 1 What DEC marketing claims "RISC" mode, perf. cache 2 2.5 All reg-to-reg inst Note the effect a cache has, that the typical VAX instruction is a complex 7 cycle one and NOT a simple 2-3 cycle one (as some have claimed), and that a VAX pretending its a RISC machine clocks in at 2 MIPS or so. 2) Complex instruction execution - the following figures compare a "VLSI VAX" (presumable a microVAX), an M68020 (16 Mhz, no wait states), and an IBM PC/RT, all executing the operation R3=4(R2)+(R1). Cache-RT is a guess for what an RT with cache would do (assumes 2 cycles for LOAD/STORE). All caches are assumed to be perfect. uVAX 68020 real-RT cache-RT time (us) 1.2 .94 1.83 .83 cycles 6 15 11 5 bytes 5 6 6 6 cycle time (ns) 200 60 170 170 instructions 1 2 3 3 scratch registers 0 0 1 1 3) Simple instruction execution - for R3=R1+R2 uVAX 68020 RT time(us) .4 .25 .17 cycles 2 4 1 bytes 3 2 2 instructions 1 1 1 microVAX's seem much more efficient (compared to an RT) at executing complex instructions than at executing simple instructions - but that's OK, since the data in (1) indicates that most VAX instructions are indeed complex. This seems due to pipelining, incidentally - a microVAX does little inter-instruction overlap (only instruction fetch/decode), which hurts the small instructions but doesn't effect the complex ones as much (so much for the claim that complex VAX instructions are less efficient than simple ones). An RT, on the other hand, pipelines its instructions. 4) Note on MIPS. IBM has been very cautious to only say that an RT is a "2 RISC MIPS" machine, but one can imagine a more "enthusiastic" company (I am NOT accusing anyone, but merely pointing out the possibility) claiming that an RT-type machine with cache was a "6-MIPS" machine, although the above data indicates that such a machine would only be 50% faster than a "1 MIPS" microVAX, and a third the speed of a "4.5 MIPS" VAX 8600. Ehud Reiter harvard!reiter.UUCP reiter@harvard.ARPA