Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: $Revision: 1.6.2.14 $; site siemens.UUCP Path: utzoo!watmath!clyde!burl!ulysses!allegra!princeton!siemens!fwb From: fwb@siemens.UUCP Newsgroups: net.arch Subject: Re: Re: Addressing modes (1702) Message-ID: <33500003@siemens.UUCP> Date: Mon, 17-Mar-86 09:51:00 EST Article-I.D.: siemens.33500003 Posted: Mon Mar 17 09:51:00 1986 Date-Received: Wed, 19-Mar-86 01:27:44 EST References: <460@ccivax.UUCP> Lines: 60 Nf-ID: #R:ccivax:-46000:siemens:33500003:000:2729 Nf-From: siemens!fwb Mar 17 09:51:00 1986 /* Written 11:12 am Mar 11, 1986 by rb@ccivax in siemens:net.arch */ /* ---------- "Re: Addressing modes (1702)" ---------- */ > For any who might remember the RCA 1702 COSMAC VIP computer, there was > a strange way to get immediate addressing. Actually, the CHIP was the 1802. I wrote, and helped to write, many K of code for this when I worked at RCA Laboratories. The native instruction set was miserable. I wrote a cross assembler with a Data General macro assembler. This let me add macro instructions to do some nice things like IF-THEN-ELSE, DO-WHILE, and 16-bit LOAD and STORE. A little program took the object module created by the DG assembler, and converted it to Intel HEX format for a prom burner. I rewrote these macros in Tek Development system macro assembler for use by other groups in the Laboratories. > If R7 was your PC register, you could say > MOV R6,(R7), and the result was the same as move imediate instruction, > because R7 would be incremented automatically. > This may have been a bug, but it was a useful bug This was not a bug. It was a feature. Really! The designers designed it as an immediate mode. > (All instructions > had to be a uniform number of cycles, and immediate mode took too many > cycles). Yes, there were 8 (or was it 16?) clocks per cpu cycle. "Why?" you ask. Well, I did too. The answer: The ALU was one bit wide! The next instruction was decoded while the computation was completed on the last one. > Actually, the 1702 had a lot of "cute" features, it would be > interesting to see a 32 bit version. Forget about a 32-bit version. I doubt that RCA (or the new GERCA) is going to make a big version based on this crummy architecture. One of the big problems with it was the D register. This was an 8-bit register which sat between memory and the 16 16-bit "scratchpad" register file. All memory references, arithmetic instructions, and I/O instructions went through this bottleneck. One of the things my macro instructions did was to hide this register as much as possible. It's too bad that I could not make it go away completely. > Does anybody familiar with this > chip consider it RISC? It was certainly a good learning tool. I guess you could say that it is a RISC if you consider the PDP-8 to be a RISC. It was an 8-bit CMOS micro which came out before the 8080. Silicon real estate was very expensive, so the designers had to make some compromises in the instruction set and operation. I hope you learned something useful. :-) ----------------------------------------------------- Frederic W. Brehm (ihnp4!princeton!siemens!fwb) Siemens Research and Technology Laboratories 105 College Road East Princeton, NJ 08540 (609) 734-3336