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From: reiter@harvard.UUCP (Ehud Reiter)
Newsgroups: net.arch
Subject: Re: RISC cache vs CISC u-code -- bogus numbers
Message-ID: <791@harvard.UUCP>
Date: Wed, 19-Mar-86 10:30:02 EST
Article-I.D.: harvard.791
Posted: Wed Mar 19 10:30:02 1986
Date-Received: Fri, 21-Mar-86 06:32:04 EST
References: <136@pyramid.UUCP> <570@imag.UUCP> <4521@think.ARPA> <777@harvard.UUCP> <634@hoptoad.uucp>
Reply-To: reiter@harvard.UUCP (Ehud reiter)
Organization: Aiken Comp Lab, Harvard
Lines: 33

In article <634@hoptoad.uucp> gnu@hoptoad.uucp (John Gilmore) writes:
>
>In article <777@harvard.UUCP>, reiter@harvard.UUCP (Ehud Reiter) writes:
>> 	2) Complex instruction execution - the following figures compare a
>> "VLSI VAX" (presumable a microVAX), an M68020 (16 Mhz, no wait states), and
>> an IBM PC/RT, all executing the operation  R3=4(R2)+(R1).
>
>I don't know the other instruction sets, but the 68020 could use
>"lea 0(a1,d2*4),a3" for 3 to 6 cycles, 4 bytes, and 1 instruction,

The operation is R3=4(R2)+(R1)  (that is, adding the memory word whose address
is R2+4 to the memory word pointed to by R1 and storing the result in R3),
not  R3=(R1+4*R2), which is what Mr. Gilmore seems to think.
     I would have preferred to give data on a more common CISC instruction,
but the above is the only one I have VAX data for.

>> 	3) Simple instruction execution - for R3=R1+R2
>
>I don't know a 68020 instruction that does this.  The 68000 series
>has few if any 3-operand instructions ...

You're absolutely right.  The figures are for R1=R1+R2 - sorry for the typo.

    In the future, if someone thinks he has found a factual mistake in a posting
of mine, I would appreciate it if he would tell me about it first, so that
simple misunderstandings (as seems to be the case with Mr. Gilmore) do not
clutter up the net.

    Thanks.

						Ehud Reiter
						harvard!reiter.UUCP
						reiter@harvard.UUCP