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Path: utzoo!utcsri!greg
From: greg@utcsri.UUCP (Gregory Smith)
Newsgroups: net.micro.68k
Subject: Re: 68000 CPU clock cycles
Message-ID: <2378@utcsri.UUCP>
Date: Fri, 21-Mar-86 13:23:30 EST
Article-I.D.: utcsri.2378
Posted: Fri Mar 21 13:23:30 1986
Date-Received: Fri, 21-Mar-86 13:34:28 EST
References: <11637@watnot.UUCP>
Reply-To: greg@utcsri.UUCP (Gregory Smith)
Organization: CSRI, University of Toronto
Lines: 32
Summary: 

In article <11637@watnot.UUCP> rwhilchie@watnot.UUCP () writes:
>Does anyone out there on the net have any information on the number of
>CPU cycles each instruction of the 68000 uses? I have the the books
>"68000 Assembly Language Programming" by Gerry Kane, Doug Hawkins, and
>Lance Leventhal; and "68000 Microprocessor Handbook" by Gerry Kane. Each
>book contains in Appendix B a table listing the CPU cycles.  The following are
>typical entries in the "Clock Cycles" column:
>
>		MOVE.L	data32,Dn	12(3/0)
>		BCS	label		10,18(1/0)
>
>Does anyone know what the two numbers inside the parenthesis mean?
>Any help would be appreciated.

The first is the number of memory 'read' cycles, and the second is the
number of write cycles. This is required because the number before the
()'s assumes 4 clock cycles per memory cycle. If your computer uses, say,
5 clock cycles for a read and 6 for a write, you have to add twice the
number of writes, and the number of reads, to allow for this. This may not
be accurate, though, because of pipelining.

We aren't writing TIMING LOOPS, now are we??? :-)

P.S. I have	BCS	label	is 10(2,0) if branch taken, 8(1,0) if not.
( for an 8-bit offset ). I believe the 2 reads for a one-word instruction
( when branch taken ) is to allow for the wasted pre-fetch of the next
instruction word.

-- 
"No eternal reward will forgive us now for wasting the dawn" -J. Morrison
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Greg Smith     University of Toronto       ..!decvax!utzoo!utcsri!greg