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Path: utzoo!utcsri!greg
From: greg@utcsri.UUCP (Gregory Smith)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <2297@utcsri.UUCP>
Date: Sun, 9-Mar-86 16:35:08 EST
Article-I.D.: utcsri.2297
Posted: Sun Mar  9 16:35:08 1986
Date-Received: Sun, 9-Mar-86 16:45:02 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp> <6780@boring.UUCP> <1162@mmintl.UUCP>
Reply-To: greg@utcsri.UUCP (Gregory Smith)
Organization: CSRI, University of Toronto
Lines: 18
Summary: 

In article <1162@mmintl.UUCP> franka@mmintl.UUCP (Frank Adams) writes:
>It seems to me that from theoretical considerations, there will always be
>*some* time dependencies in any device.  If you run it with a fast enough
>processor, it will stop working.

False. A processor-to-device interface can be designed in such a way that
an access to a slow device will cause the processor to be 'stopped' until
the device is ready. This can be done in a port-dependent way, i.e. if
there is only one slow device on the bus, the processor will only be
slowed when that device is accessed. The 'stopped' state of the processor
is sometimes called a 'wait' state.
On many systems, this technique is the rule rather than the exception -
I think UNIBUS is an example.

-- 
"So this is it. We're going to die."	- Arthur Dent
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Greg Smith     University of Toronto       ..!decvax!utzoo!utcsri!greg