Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site duke.UUCP Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!mcnc!duke!rrt From: rrt@duke.UUCP (Russell R. Tuck) Newsgroups: net.sources.d Subject: Wanted: enhanced Make Message-ID: <7013@duke.UUCP> Date: Fri, 14-Mar-86 14:58:13 EST Article-I.D.: duke.7013 Posted: Fri Mar 14 14:58:13 1986 Date-Received: Sun, 16-Mar-86 00:46:43 EST Organization: Duke University Lines: 28 I am looking for a program that will extend make's functionality by letting me parameterize my makefiles. An extended version of make with a #include statement for use in makefiles might work, or an even more general program might be needed. As an example, I keep each module of a large program in a separate directory. Each module (directory) has its own makefile, and I want these makefiles to share a set of common definitions. When I change the common definitions, I want the changes to automatically take effect in each makefile. Some of these definitions are macros, and some are rules. I also have a program (taken from net.sources some time ago) that reads source files and generates a list of the files they depend on, in "make" form. I want to include these generated dependencies in the makefile that actually makes each module. A file include facility in makefiles would solve the first problem, but I think a second level of makefile is necessary for the second. (I.e., the first makefile builds a second makefile containing the generated dependencies, then runs make on this second makefile to make the module object library.) Please mail your ideas, suggestions, or programs to me, and I will post a summary if there is sufficient interest. Russ -- Russell R. Tuck, III Computer Science Department Duke University, Durham, NC 27705 CSNET: rrt@duke ARPA: rrt%duke.csnet@csnet-relay UUCP: {ihnp4|decvax|mcnc}!duke!rrt VOICE: (919) 684-5110 ext.27