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From: ken@turtlevax.UUCP (Ken Turkowski)
Newsgroups: net.arch,net.micro.68k
Subject: Re: Re: risc questions [really, smart I cache from ancient history]
Message-ID: <1107@turtlevax.UUCP>
Date: Mon, 7-Apr-86 13:32:17 EST
Article-I.D.: turtleva.1107
Posted: Mon Apr  7 13:32:17 1986
Date-Received: Wed, 9-Apr-86 22:38:53 EST
References: <1511@decwrl.DEC.COM> <5100028@ccvaxa> <401@mips.UUCP> <273@garth.UUCP> <420@mips.UUCP> <175@ima.UUCP> <208@valid.UUCP>
Reply-To: ken@turtlevax.UUCP (Ken Turkowski)
Followup-To: net.micro.68k
Organization: CIMLINC, Inc. @ Menlo Park, CA
Lines: 18
Xref: watmath net.arch:2997 net.micro.68k:1613

In article <208@valid.UUCP> gelfand@valid.UUCP (Brooks Gelfand) writes:
>The Motorola 68010 has a loop mode operation that works with the
>DBcc instruction. In this case the loop is only one instruction deep.

There are even further restrictions; you can do a block copy
	L:	movl a0@+,a1@+
	dbra	d7,L
but you can't poll an I/O device's busy bit
	M:	btst #3,a0@
	dbeq	d7,M
and still remain within the cache.

Does anybody know why Motorola doesn't allow just any instruction
that will fit?
-- 
Ken Turkowski @ CIMLINC, Menlo Park, CA
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