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From: kevin@sun.uucp (Kevin Sheehan)
Newsgroups: net.arch,net.micro.68k
Subject: Re: 68k dbcc
Message-ID: <3479@sun.uucp>
Date: Thu, 10-Apr-86 14:38:42 EST
Article-I.D.: sun.3479
Posted: Thu Apr 10 14:38:42 1986
Date-Received: Sat, 12-Apr-86 00:02:15 EST
References: <1511@decwrl.DEC.COM> <5100028@ccvaxa>
Organization: Sun Microsystems, Inc.
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Xref: linus net.arch:2775 net.micro.68k:1530

> There are even further restrictions; you can do a block copy
> 	L:	movl a0@+,a1@+
> 	dbra	d7,L
> but you can't poll an I/O device's busy bit
> 	M:	btst #3,a0@
> 	dbeq	d7,M
> and still remain within the cache.
> 
> Does anybody know why Motorola doesn't allow just any instruction
> that will fit?
> -- 
> Ken Turkowski @ CIMLINC, Menlo Park, CA

	the loop mode works by using the instruction prefetch register to
hold the instruction. This means only instructions that are 16 bits TOTAL
can use loop mode - fortunately, that includes most of the useful ones.

	the only answers I ever got to "why dont the other 16 bit instructions
do it too" was something about not being able to do RMW write cycles, and
"internal path/ALU limitations", although the latter still seems like a glib
answer.  Anybody at MOT have an answer?

			l & h,
			kev