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Path: utzoo!watmath!clyde!cbosgd!ihnp4!ihwpt!knudsen
From: knudsen@ihwpt.UUCP (mike knudsen)
Newsgroups: net.arch
Subject: Re: ORed indexes
Message-ID: <828@ihwpt.UUCP>
Date: Tue, 22-Apr-86 14:52:07 EST
Article-I.D.: ihwpt.828
Posted: Tue Apr 22 14:52:07 1986
Date-Received: Wed, 23-Apr-86 23:44:34 EST
References: <5100066@ccvaxa>
Organization: AT&T Bell Laboratories
Lines: 32


> How would you react to an instruction set that had no indexed addressing
> mode, but did have a mode where a register was ORed into the address?
> 
> Well, there you have it: ORed indexes. Tell me I'm brain damaged.
> 
> Andy "Krazy" Glew. Gould CSD-Urbana.    USEnet:  ihnp4!uiucdcs!ccvaxa!aglew
> 1101 E. University, Urbana, IL 61801    ARPAnet: aglew@gswd-vms

Nah, your brain is OK.  I built a special-purpose (but sorta
general architecture) computer out of STTL to run at 10 MHz
about 5 years ago.  Each instruction completes in 100 nsec,
for you RISC freaks.  No branching or access delays are needed,
tho each memory write overlaps with the next instruction's decode.

It controls 64 identical hardware items, so there are several
arrays of 64 words each.  So YES, I do OR'ed indexing.
The low 6 bits of my pointer registers are ORed with
constant bases which select which array gets accessed.
(This is just the reverse of structure fields, where constant
offsets are added to *big* pointers.)

Actually, all 12 of my index bits are significant.
This allows 128, 256, ... -word arrays if they are aligned
on the proper boundaries.  Also my assembler for the machine
supports "free-basing" where the ORed base is zero so the
index accesses the whole 4K of RAM randomly.
(My term free-basing has since been expropriated, but
I claim Pryority in the matter.  The 3 boards get hot as
Hades but have never caught fire, or even failed in
4 years of operation.)
	mike k