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From: eric@chronon.UUCP (Eric Black)
Newsgroups: net.arch
Subject: Re: How Many Virtual Spaces
Message-ID: <227@chronon.chronon.UUCP>
Date: Wed, 23-Apr-86 16:18:51 EST
Article-I.D.: chronon.227
Posted: Wed Apr 23 16:18:51 1986
Date-Received: Sat, 26-Apr-86 03:34:42 EST
References: <5100037@ccvaxa> <5100040@ccvaxa> <6581@utzoo.UUCP> <909@umd5.UUCP> <7711@watdaisy.UUCP>
Reply-To: eric@chronon.UUCP (Eric Black)
Organization: Chronon Computer Corp., Mtn. View, CA
Lines: 30

In article <7711@watdaisy.UUCP> dneudoerffer@watdaisy.UUCP (Dave Neudoerffer) writes:
>I think we need some clarification on what cache we're talking about here.
>I agree with Henry that a process identification tag on addresses
>in the memory management translation cache (TLB) is a bonus and saves
>flushes of this cache.
>Also if a data cache is used between processor and memory management, 
>ie caching virtual addresses, then this tag may also be useful.  However,
>as Ben points out, you can get physical address aliasing if two
>processes are accessing the some memory page.
>However, if a data cache is put in the system after the memory management
>hardware, there is no aliasing problem since only physical addresses
>are being cached.  I beleive this last setup is the one found in most
>systems with a data cache.
>

Ah, but putting the cache AFTER the memory management hardware puts
the address translation in the critical path for ALL memory accesses,
whether the reference hits the cache or not.

Too bad if TLB lookup (or whatever) is more than an insignificant fraction
of cache access time.  It is easier to implement, though.  Of course,
if the processor is slow enough that time(TLB+cache) is still quick from
the processor's point of view, it doesn't matter.  Nobody would ever
want to buy a faster processor, would they? :-)

-- 
Eric Black   "Garbage In, Gospel Out"
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