Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!decwrl!pyramid!pesnta!hplabs!hpda!hpisoa2!hpitg!lll-crg!brooks@lll-crg
From: brooks%lll-crg@lll-crg.UUCP
Newsgroups: net.arch
Subject: Re: Response to <1363@unc.unc.UUCP> <1712@gitpyr.UUCP>
Message-ID: <1418@lll-crg>
Date: Fri, 2-May-86 08:53:00 EDT
Article-I.D.: lll-crg.1418
Posted: Fri May  2 08:53:00 1986
Date-Received: Sun, 11-May-86 15:45:18 EDT
References: <1363@unc>
Lines: 14

In article <315@garth.UUCP> kissell@garth.UUCP (Kevin Kissell) writes:
>Indeed, if cycle time is truly a function of circuit technology,
>one wonders how Seymour Cray has managed to get such fast cycle times
>with technology that he gleefully admits was a generation behind the
>state of the art.  Cycle time is as much a function of architecture
>as of technology - it's not just how fast your transistors switch,
>it's also how few of them you can get away with stringing together in 
>each logic stage.
Seymour Cray gets fast cycle times the good old fashioned way, no
microde and pipeline everything in sight, including the channel
to main memory.   Now that Micro makers have finally started picking
up on the fundamentally important load/store RISC ideas, they had better
start looking at pipelining the functional units of the cpu along with the
channel to main memory if they want more speed.