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From: jewett@hplabsc.UUCP (Bob Jewett)
Newsgroups: net.crypt
Subject: RSA chip, 40kbit/sec, 512-bit code
Message-ID: <28000001@hplabsc.UUCP>
Date: Tue, 22-Apr-86 14:07:00 EST
Article-I.D.: hplabsc.28000001
Posted: Tue Apr 22 14:07:00 1986
Date-Received: Thu, 24-Apr-86 05:06:21 EST
Organization: Hewlett-Packard Laboratories - Palo Alto, CA
Lines: 13

From the advance program for the Custom Integrated Circuits
Conference,  Rochester NY, May 12-15 1986, page 39:

A Fast Asynchronous RSA Encryption Chip

G. Orton, L.E. Peppard, S.E. Tavares, Queen's Univ., Kingston, Ontario,
Canada

This RSA key encryption chip uses asynchronous modulo multiplication
to improve the throughput by a factor of 40 relative to a synchronous
implementation.  The chip is capable of an average throughput of
40 Kbit/sec for 512 bit encryption with a 2-micron CMOS process and a
1 square cm die area.