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From: markp@valid.UUCP (Mark P.)
Newsgroups: net.micro.68k
Subject: Re: 68040
Message-ID: <383@valid.UUCP>
Date: Thu, 26-Jun-86 16:58:59 EDT
Article-I.D.: valid.383
Posted: Thu Jun 26 16:58:59 1986
Date-Received: Wed, 2-Jul-86 03:33:14 EDT
References: <8606110823.AA02156@pavepaws> <543@ihlpf.UUCP>
Organization: Valid Logic, San Jose, CA
Lines: 34

> > 
> > 	128 bit internal busses are not likely for high level assembly.
> > It is more reasonable for low level microcode (maybe they were talking about
> > microcode in wherever_you_got_the_gossip_from)
> > 
> > 					-Matt
> 
> I don't know where he got the info, but I saw such a piece
> of rumor in a recent "EE Times".  It said 32-bit external
> and 128-bit internal.  I'm pretty suret that they said
> that the registers were going to be 128 bits wide.
> 
> -- 
> Stuart Ericson                       Disclaimer: My computer wrote
>                                                  this - I just didn't
>                                                  have the heart to
> USENET: ..!ihnp4!ihlpf!stuart                    turn it off.
> voice: (312) 979-4288
> 
> "This time I'm switchin' to glide..."

A more likely scenario is 16-byte cache lines (128 bits, get it?).
An unsophisticated EE Times interpretation of such a rumor would
probably get printed as "128-bit internal architecture", and this has
got to be a much more likely possibility.  128-bit registers are
just NOT useful enough to warrant the extra carry-lookahead delay,
space, etc.

			Mark Papamarcos
			Valid Logic Systems, Inc.
			{hplabs,pyramid,ihnp4,...}!pesnta!valid!markp

disclaimer: rumors are rumors, especially when filtered through trade rags,
	    and the above are only my opinions.