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From: Cent.Mbeck%OZ.AI.MIT.EDU@mit-xx.ARPA (Mark Becker)
Newsgroups: net.micro.cpm
Subject: Hardware CAUTION: XOR S-100 CPU Board (Rev. B)
Message-ID: <1440@brl-smoke.ARPA>
Date: Tue, 17-Jun-86 20:45:47 EDT
Article-I.D.: brl-smok.1440
Posted: Tue Jun 17 20:45:47 1986
Date-Received: Sat, 21-Jun-86 09:19:39 EDT
Sender: news@brl-smoke.ARPA
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     This CPU board has a >50 nsec. glitch on the phase 1 (pin 25)
line due to a race condition between IC-8D (a 7474) and IC-12A (a
74LS04) being caught by IC-5D (a 74LS02) and then amplified by IC-3A
(a 74LS367).

     The fix is two-fold: (1) Replace IC-8D with a 74LS74.  This will
narrow the glitch such that a... (2) small capacitor installed between
IC12 pin 2 and ground.  I found, after some experimenting, that 150 pF
worked find - glitch now gone.

     Two CPU boards here had this problem.  The extra pulse out was
causing timing problems on another board in the frame which was using
phase 1 clock to generate internal timing.

     I would appreciate hearing from other XOR S-100 owners - there
are some mistakes in the schematics I received from U.S. Micro Sales
and a couple of problems in the CP/M BIOS they shipped with early
systems.

Mark Becker
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