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From: bjorn@alberta.UUCP (Bjorn R. Bjornsson)
Newsgroups: net.micro.ns32k
Subject: Re: Re: National's 32332 (Apples and oranges really)
Message-ID: <942@alberta.UUCP>
Date: Thu, 12-Jun-86 23:26:42 EDT
Article-I.D.: alberta.942
Posted: Thu Jun 12 23:26:42 1986
Date-Received: Sat, 14-Jun-86 16:15:20 EDT
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Organization: U. of Alberta, Edmonton, AB
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In <88@intelca.UUCP> clif@intelca.UUCP (Clif Purkiser) writes:
> After reading the data sheet and other information on the part I am only
> aware of a few improvements made to the 32332 vs 32032.
>	1. Burst Mode Bus, useful for cache systems and possibly
>	   DMA-like transfers
>	2. 32 address lines, no performance increase
>	3. large prefetch unit, some performance boost.

The speed improvements (32332 over 32032) come from:

	1. Separate address path ALU with barrel shifter.
	   As with the 80286 vs 8086, the extra addressing hardware
	   is responsible for a major part of the performance gains.

	2. Burst mode bus, Transfers upto 16 bytes on operand reads
	   and instruction prefetch.

	3. 20 byte prefetch queue (vs. 8 bytes for the 32032).

	4. Slight microcode improvements.

In a system implementation additional improvements
from the following:

	a) In memory managed systems, there is 1 less clock per
	   bus cycle, ie. 4 (vs. 5).
	b) Pages are 4k bytes (vs. 512).
	c) MMU has 32 bit data bus (vs. 16) (for TLB misses).
	d) Slave processors use 32 bit transfers.



			Bjorn R. Bjornsson
			Department of Computing Science
			University of Alberta
			Edmonton

			ihnp4!alberta!bjorn