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From: lee@nscpdc.UUCP (Lee Tapper)
Newsgroups: net.micro.ns32k
Subject: Re: Re: Re: Re: Re: National's 32332 (Apples and oranges really)
Message-ID: <577@nscpdc.UUCP>
Date: Sat, 21-Jun-86 13:54:41 EDT
Article-I.D.: nscpdc.577
Posted: Sat Jun 21 13:54:41 1986
Date-Received: Tue, 24-Jun-86 03:45:05 EDT
References: <869@hoptoad.uucp> <428@cbmvax.cbmvax.cbm.UUCP>
Reply-To: lee@nscpdc.UUCP (Lee Tapper)
Organization: NSC Portland Development Center, Portland Oregon
Lines: 27

In article <428@cbmvax.cbmvax.cbm.UUCP> daveh@cbmvax.cbm.UUCP (Dave Haynie) writes:
>
>I did say clock speed, STUPID ME.  What I MEANT was bus speed, which is one
>of the mosy meaningful measures I can come up with, since much of the cost of
>a system is based on the speed you run the bus at.  A 68000 at 8MHz runs a
>2MHz bus, I though that the 8086 at 8MHz was very similar.  I don't know the
>ratio of clock to bus speed on the 32K series, but I think its more like 
>5:1 than 4:1; anyone know for sure?

Bus speed for the 332 depends on a number of factors. The
first is the presence or absence of an MMU. The second is
the bus cycle type. The 332 has the ability to take all of
it's instruction stream and any misaligned operands in burst
mode. In this mode it sends out an address and then gets the
next four 32 bit words back to back without using any bus time
for additional addresses. This works quite well for nibble mode
memory chipsand can speed execution. The ratios of
clocks to bus time are as follows :

* no MMU, single cycle 3:1
* MMU, single cycle 4:1
* no MMU burst fetch 9:4

Lee Tapper


* MMU burst fetch 10:4