Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utcs!mnetor!seismo!ll-xn!nike!oliveb!glacier!navajo!rokicki From: rokicki@navajo.UUCP Newsgroups: net.micro.amiga Subject: Re: Deceit Message-ID: <740@navajo.STANFORD.EDU> Date: Wed, 16-Jul-86 16:55:57 EDT Article-I.D.: navajo.740 Posted: Wed Jul 16 16:55:57 1986 Date-Received: Thu, 17-Jul-86 19:48:22 EDT Organization: Stanford University Lines: 53 Keywords: apology [ Snugglebunnies! Snugglebunnies! Snugg~|% Well, I just received a nice letter in response to my earlier flame, so, after receiving Richard Rodgers' permission, I quote: -------------------------------------------------------- In article <737@Navajo.ARPA> you write: > >I've got one of those CardCo boards, and yes, it does slow the machine >down something awful. Here are the stats: > >Which means I just paid so many hundreds of dollars to SLOW DOWN MY >MACHINE! Now, I've designed memory boards before; it's not that >difficult to make the RAM run with no wait states on a 7.2 MHz > As president of the company that designed the C Ltd. (CardCo) board I offer my humblest apology. It would seem that a last second PAL change did in fact make it into the final product without adequate testing. The problem is currently being fixed, and the boards that did get out will be updated. Not to justify, but to explain how this happened. None of our (10+) beta testers found this problem. The excessive wait states do not occur 100% of the time. Our logic analyzer hard copy was "lucky" enough to catch a one wait state picture. We then shipped 150 or so boards before the problem was caught. You got one of our 150 boards, and reported the problem a day after we had found it. You probably called C Ltd., and were frustrated by the lack of answers you received. Sorry... If you will send me your name, address, and/or phone number, I will personally see that you get an updated PAL as soon as it becomes available. I would also like to stress that the board will probably still run with one wait state. The reason for this wait state is that we had to "glue" an Intel chip onto a Motorolla bus. The Intel chip was chosen because it was the only CMOS DRAM controller we could find. A CMOS chip was necessary to accomadate the internal power specifications. A one wait state memory board will NOT be a problem for 98%+ of our customers, so was approved. Richard N. Rodgers, President Creative Microsystems Inc. 9140 SW Locust Street Tigard, OR 97223 -------------------------------------------------------- Made me feel better, anyway, that something was being done about it. I have also learned that their expansion cage and it's memory card does not require any wait states. I've been getting around the problem somewhat by forcing my programs into chip memory with a linker option. True, one wait state is still perhaps too much, but I'm sure I'll survive until I can afford an expansion cage. -tom