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From: radford@calgary.UUCP
Newsgroups: net.arch
Subject: Where are delayed branches handled?
Message-ID: <299@vaxb.calgary.UUCP>
Date: Sun, 10-Aug-86 18:19:43 EDT
Article-I.D.: vaxb.299
Posted: Sun Aug 10 18:19:43 1986
Date-Received: Tue, 12-Aug-86 17:06:47 EDT
Organization: U. of Calgary, Calgary, Ab.
Lines: 11

Something I've wondered about:

On RISC machines with delayed branches, who does the instruction
rearrangement that tries to put useful instructions after the branch?

Obvious possibilities are the assembler or the compiler. Does anyone
know whether the compiler can do a significantly better job than 
the assembler? (I'm assuming the compiler generates assembler code.)

    Radford Neal
    The University of Calgary