Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!watmath!clyde!caip!nike!oliveb!glacier!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: net.arch Subject: Re: Where are delayed branches handled? Message-ID: <627@mips.UUCP> Date: Sat, 16-Aug-86 17:17:44 EDT Article-I.D.: mips.627 Posted: Sat Aug 16 17:17:44 1986 Date-Received: Sun, 17-Aug-86 09:45:16 EDT References: <299@vaxb.calgary.UUCP> <612@mips.UUCP> <187@ima.UUCP> Reply-To: mash@mips.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 17 In article <187@ima.UUCP> johnl@ima.UUCP (John R. Levine) writes: >In the AIX C compiler for the RT PC, we handled the delayed branches in the >peepholer for the compiler. >The peepholer seemed to be the best place because it could make assumptions >about the kind of code emitted by the compiler. Doing the right thing was >a little tricky because only about half of the RT's instructions change the >condition code, and you had to look back in the instruction stream .... 1) It's good to see more data: there seems to be a consensus that reorganization is either in the assembler or very late (peephole time) in the compiler. 2) The condition code note is interesting: it's exactly this kind of thing that encouraged us to remove any trace of condition codes! -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086