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From: guy@sun.uucp (Guy Harris)
Newsgroups: net.arch
Subject: Re: VERY LARGE main memories
Message-ID: <6611@sun.uucp>
Date: Wed, 27-Aug-86 15:50:44 EDT
Article-I.D.: sun.6611
Posted: Wed Aug 27 15:50:44 1986
Date-Received: Thu, 28-Aug-86 08:45:24 EDT
References: <2017@sdcsvax.UUCP> <884@gilbbs.UUCP>
Organization: Sun Microsystems, Inc.
Lines: 14

>    Someone please correct me if I am wrong, but as I have been lead to 
> understand the situation, it will prove somewhat difficult to successfully
> implement large physical memory systems on the order of 1Gb.  The primary
> impediment seems to be the delays caused by propagation delays in the
> decoding trees.   Anyone care to enlight me (us)?

"Will prove"?  As *I* have been lead to understand the situation, the Cray-2
is *already* offering primary memories of that size.  From your reference to
"decoding trees", I presume you're talking about *single chip* memories of
that size, not memory systems.
-- 
	Guy Harris
	{ihnp4, decvax, seismo, decwrl, ...}!sun!guy
	guy@sun.com (or guy@sun.arpa)