Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site petrus.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!bellcore!petrus!hammond
From: hammond@petrus.UUCP (Rich A. Hammond)
Newsgroups: net.arch
Subject: Re: VERY LARGE main memories
Message-ID: <289@petrus.UUCP>
Date: Thu, 28-Aug-86 08:35:40 EDT
Article-I.D.: petrus.289
Posted: Thu Aug 28 08:35:40 1986
Date-Received: Fri, 29-Aug-86 08:33:49 EDT
References: <2017@sdcsvax.UUCP> <884@gilbbs.UUCP>
Organization: Bell Communications Research, Inc
Lines: 24

> 
tom keller writes:
>    Someone please correct me if I am wrong, but as I have been lead to 
> understand the situation, it will prove somewhat difficult to successfully
> implement large physical memory systems on the order of 1Gb.  The primary
> impediment seems to be the delays caused by propagation delays in the
> decoding trees.   Anyone care to enlight me (us)?

Well, the Cray 2 supports 256M Word (where word = 64 bits) i.e. 2 Gb,
so it is not impossible.  The decoding trees grow as the log of the
size of memory, so it isn't bad.  Plus, one rarely treats memory as a
single byte, one selects a larger chunk (1 to n words, each word of 4
or 8 bytes), gets it to the CPU and then uses a barrel shifter or other
select to pick out the individual byte(s) wanted.  Clearly, the decoding
times would get longer if we stayed with the same technology, but the
memory IC's are also getting faster as they shrink the circuit size.
e.g. the 64k rams had access times around 100-120 ns, the 256k rams had
access times around 80-100ns, the 1M rams have access times around 60-80ns.
This despite the increase in decoding on the chips.  So, going to the
larger chips allows both the 4fold increase from the chips, plus there
is additional time available for external decoding (assuming the memory cycle
stays constant).

Rich Hammond	hammond@bellcore.com