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From: awpaeth@watcgl.UUCP (Alan W. Paeth)
Newsgroups: net.arch
Subject: Zero memory in 1 second / CG Bell
Message-ID: <933@watcgl.UUCP>
Date: Fri, 29-Aug-86 13:45:42 EDT
Article-I.D.: watcgl.933
Posted: Fri Aug 29 13:45:42 1986
Date-Received: Sat, 30-Aug-86 01:18:33 EDT
References: <1130@bu-cs.bu-cs.BU.EDU>
Reply-To: awpaeth@watcgl.UUCP (Alan W. Paeth)
Organization: U of Waterloo, Ontario
Lines: 16

With regards to Shein's law (zeroing memory in N seconds):

I heard DEC's VP of research, C. Gordon Bell while at Caltech in 1976. As part
of his guest lecture (discussing PDP11 architecture), he commented that a
memory which cycled in 1uS gave rise to 1 Meg as a reasonable upper bound for
storage, with memory size and access time trading off in direct proportion
for other values. Ivan Sutherland (CS chairman at the time) then proposed
that a maxim for good design was "being able to initialize memory in one
second", and Bell agreed. This is really a bandwidth measure, as the memory
is presumably filled via DMA, if it is to run at its full bandwidth.  It is
useful as a measure of CPU speed assuming that the CPU cycles at rates
comparable to the main memory cycle time (which may not be true with
architectures with huge memories a/o multiprocessors). This could account for
a factor of N on newer designs. 

    /Alan Paeth, University of Waterloo