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From: ian@cbosgd.UUCP (Neil Kirby)
Newsgroups: net.arch
Subject: Re: Very large memories
Message-ID: <2494@cbosgd.UUCP>
Date: Fri, 29-Aug-86 15:42:02 EDT
Article-I.D.: cbosgd.2494
Posted: Fri Aug 29 15:42:02 1986
Date-Received: Sat, 30-Aug-86 03:25:25 EDT
Organization: AT&T Bell Laboratories, Columbus, Oh
Lines: 19


	A quick and dirty way to put the decoding delay into perspective is
to think about the decoding delays back in the days when people thought about
building 1M of ram using 1K chips.  Using the same amount of decoding logic
you can build 1G out 1M chips.  Not only that, but the speeds of the decoders
and the memories both have improved since then.  Now I don't know if anyone
actually built 1M memories out of 1K chips, I was in high school then.  The
solution then is likely to still be valid (even if it was to wait for chips
to get bigger).

	Paging the 1G of memory IS a potential problem.  Most pagers run in
the order of n squared where n is the number of pages.  Using the same or
nearly the same page size and gigabyte memories instead of megabyte memories
gives a slowdown factor of about a million.  Even an order n pager takes a
slowdown factor of a thousand.  Hardware help and/or new algorithms will be
needed.  

		Neil Kirby
		...cbosgd!ian