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From: dwc@hou2b.UUCP (D.CHEN)
Newsgroups: net.arch
Subject: paging
Message-ID: <826@hou2b.UUCP>
Date: Wed, 3-Sep-86 04:23:24 EDT
Article-I.D.: hou2b.826
Posted: Wed Sep  3 04:23:24 1986
Date-Received: Wed, 3-Sep-86 21:28:25 EDT
Organization: AT&T Bell Labs, Holmdel NJ
Lines: 26


>[Time required for virtual memory mapping in huge memory systems]

>How about increasing the page size proportionally to the memory
>size.  If you got gigabytes to burn what's wrong with a 1 meg page?

one thing that has to be considered then is disk transfer rate.
while there is not too much difference in transfer times for .5K
and 4K pages, a 1M page will take a substantial amount of time to
load.

without thinking too much, the problem looks like it would be solved
with a corresponding growth in address translation buffer size.
it locality of reference still applies in those applications using
large address spaces, then the growth in the address translation
buffer need not even be linear in address space size.

danny chen
ihnp4!hou2b!dwc

by the way, i don't even think that page table management scheme
need be quadratic or linear with page table size.  i can think of
at least a couple of schemes that are more or less constant.  it is
interesting though that all the popular paging strategies taught in
school do exhibit poor behavior when used with large address spaces
and/or large memories.