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From: aglew@ccvaxa.UUCP
Newsgroups: net.arch
Subject: Delayed Loads
Message-ID: <5100133@ccvaxa>
Date: Sat, 13-Sep-86 18:57:00 EDT
Article-I.D.: ccvaxa.5100133
Posted: Sat Sep 13 18:57:00 1986
Date-Received: Sun, 14-Sep-86 20:12:52 EDT
Lines: 21
Nf-ID: #N:ccvaxa:5100133:000:808
Nf-From: ccvaxa.UUCP!aglew    Sep 13 17:57:00 1986


There has been some discussion of delayed branches in this newsgroup;
can anybody say anything useful about delayed load/stores? Ie. memory
access functions that are defined to work the same way as delayed
branches, not to take effect until after a few more instructions.

Eg.:	memaddr: .word 2

	LOAD r0 := #1
	LOAD r0 := [memaddr]
	MOV r1 := r0		-- r1 contains 1, not 2
	MOV r2 := r0		-- r2 contains 2, the load has completed

Or, the contents of r0 might be undefined on the second load. This might
be preferable, since it would mean that, if you could eventually build a
faster memory system that completes in one cycle, you could use it.

What systems use these?

Andy "Krazy" Glew. Gould CSD-Urbana.    USEnet:  ihnp4!uiucdcs!ccvaxa!aglew
1101 E. University, Urbana, IL 61801    ARPAnet: aglew@gswd-vms