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From: stubbs@ncr-sd.UUCP (Jan Stubbs)
Newsgroups: net.arch
Subject: Re: Delayed Loads
Message-ID: <1174@ncr-sd.UUCP>
Date: Thu, 18-Sep-86 18:08:27 EDT
Article-I.D.: ncr-sd.1174
Posted: Thu Sep 18 18:08:27 1986
Date-Received: Fri, 19-Sep-86 23:58:29 EDT
References: <5100133@ccvaxa>
Reply-To: stubbs@ncr-sd.UUCP (0000-Jan Stubbs)
Organization: NCR Corporation, San Diego
Lines: 25

In article <5100133@ccvaxa> aglew@ccvaxa.UUCP writes:
>
>can anybody say anything useful about delayed load/stores? Ie. memory
>access functions that are defined to work the same way as delayed
>branches, not to take effect until after a few more instructions.
>
>What systems use these?
>Andy "Krazy" Glew. Gould CSD-Urbana.    USEnet:  ihnp4!uiucdcs!ccvaxa!aglew

NCR 8500 (circa 1975) and 8600 (circa 1979)is one such machine made with 100K
ECL, 56 and 38 nanosecond cycle time repectively, one instruction per
cycle. It  has a fetch instruction which gives an address to fetch in 
one of its 64 registers, and a place to load it in another register. 
You may execute dozens of other instructions including three more fetches 
while waiting for the contents of memory to show up in the specified register, 
but if you reference that register the pipeline hangs till the word shows up.


The NCR/32 Microprocessor (circa 1982) is similar except you first do a Fetch,
then later you specify the destination to load it with a Receive instruction,
which hangs the pipeline if it isn't ready. You can put any instruction
except a fetch or store between the fetch and receive.

I believe most "RISC" machines (Pyramid, MIPS, Motorola 78000) do this
somehow or other.