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From: dyer@atari.UUcp (Landon Dyer)
Newsgroups: net.micro.atari16,net.micro.amiga,net.micro.68k
Subject: Re: 68000 Memory Managment
Message-ID: <417@atari.UUcp>
Date: Thu, 21-Aug-86 11:53:05 EDT
Article-I.D.: atari.417
Posted: Thu Aug 21 11:53:05 1986
Date-Received: Fri, 22-Aug-86 05:58:59 EDT
References: <508@elmgate.UUCP> <64@mit-prep.ARPA> <510@elmgate.UUCP> <4374@gatech.CSNET>
Organization: Atari Corp., Sunnyvale CA
Lines: 31
Keywords: 68000 atari amiga 68k mmu
Xref: mnetor net.micro.atari16:1672 net.micro.amiga:4354 net.micro.68k:1150

In article <4374@gatech.CSNET>, jeff@gatech.CSNET (Jeff Lee) writes:
>                                                 You could do
> the same with a 68000. With a couple of 35ns rams and some address
> decoding (to map them into memory) you can implement a similar type of
> MMU. For system level access, you bypass the rams and physical and logical
> memory are the same. The OS loads the memory mapping rams with the
> appropriate address and dispatches the process. While in user mode, the
> high order bits are remapped into different physical locations (going
> through the MMU rams). You access something that you are not supposed
> to and you take a bus error.

It's a nice idea in general . . . but not on the ST.  Address
timing is *so* critical that running the address lines through a
35ns RAM would result in missing RAS and/or CAS windows on the
DRAMs.  Bad things happen.

The other gotcha is that by the time the lookup RAM can indicate
if a location should generate a bus error, the memory controller
is already comitted to the read or write cycle.  You'd have to
map every unused page to some piece of scratch RAM.

We looked at this many months ago, and went a different route....

-- 

-Landon Dyer, Atari Corp.		{sun,lll-lcc,lll-crg!vecpyr}!atari!dyer

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