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From: jeff@gatech.CSNET (Jeff Lee)
Newsgroups: net.micro.atari16,net.micro.amiga,net.micro.68k
Subject: Re: 68000 Memory Managment
Message-ID: <4422@gatech.CSNET>
Date: Sat, 30-Aug-86 23:48:29 EDT
Article-I.D.: gatech.4422
Posted: Sat Aug 30 23:48:29 1986
Date-Received: Sun, 31-Aug-86 05:07:51 EDT
References: <508@elmgate.UUCP> <64@mit-prep.ARPA> <510@elmgate.UUCP> <417@atari.UUcp> <271@dmsd.UUCP> <937@cit-vax.Caltech.Edu>
Reply-To: jeff@gatech.UUCP (Jeff Lee)
Organization: School of Information and Computer Science, Georgia Tech, Atlanta
Lines: 23
Keywords: 68000 atari amiga 68k mmu
Xref: mnetor net.micro.atari16:1777 net.micro.amiga:4474 net.micro.68k:1182

In article <937@cit-vax.Caltech.Edu> wen-king@cit-vlsi.UUCP (Wen-King Su) writes:
>                         The high speed CAS only block transfer
>operation available in many DRAMs is rendered useless since contiguous
>column addresses in a DRAM chip are no longer contiguous in 68K's
>address space.

If you are talking about nibble-accessible rams, the ones that I saw
operate only on mod-4 boundaries and each time you strobe the CAS they
return the next bit circularly (mod-4). Since the memory management
schemes that I am familiar with use 2^N boundaries (N > 2), this should
be no problem. But then, you might be talking about another (even newer)
type of ram that I'm not familiar with.

Speaking of which, does anyone know of a REAL (ie - available off the
shelf, now) system that actually uses the nibble mode of some of the
newer rams. It looks like a great way to load your cache quickly with
some of the bus-hog multiprocessors that are becoming available now
(Encore, Sequent, etc...). They already load 64 bits of memory at a time
onto the separate processor cards when they need to hit main memory.
-- 
Jeff Lee
CSNet:	Jeff @ GATech		ARPA:	Jeff%GATech.CSNet @ CSNet-Relay.ARPA
uucp:	...!{akgua,allegra,hplabs,ihnp4,linus,seismo,ulysses}!gatech!jeff