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From: jnw@mcnc.UUCP (John White)
Newsgroups: net.micro.atari16,net.micro.amiga,net.micro.68k
Subject: Re: 68000 Memory Managment
Message-ID: <480@mcnc.mcnc.UUCP>
Date: Fri, 12-Sep-86 22:44:40 EDT
Article-I.D.: mcnc.480
Posted: Fri Sep 12 22:44:40 1986
Date-Received: Sat, 13-Sep-86 21:07:44 EDT
References: <508@elmgate.UUCP> <64@mit-prep.ARPA> <510@elmgate.UUCP> <823@navajo.STANFORD.EDU>
Organization: Microelectronics Center of NC; RTP, NC
Lines: 50
Summary: proof of obviosity
Xref: mnetor net.micro.atari16:1938 net.micro.amiga:4645 net.micro.68k:1219

In article <823@navajo.STANFORD.EDU>, rokicki@navajo.STANFORD.EDU (Tomas Rokicki) writes:
> In article <6985@sun.uucp>, ludemann@sun.uucp (Jim Ludemann) writes:
> > I hate to tell you folks, but Andy Bechtolsheim here at Sun has a patent 
> > (applied for and granted) on using the untranslated addresses as the 
> > RAS addresses and doing the MMU address translation before the column 
> > addresses are needed for CAS.  Sooner or later, it's going to cost some
> > competitors a WHOLE lot of money.
> 
> How the hell can the patent office grant patents like this?  It's sort
> of like patenting the idea of grounding DTACK on a 68000 or putting
> chocolate ice cream in root beer; the idea is too obvious.  To coin a
> phrase, it's patently ridiculous.
> 

     I don't think that you will convince many people that something is
obvious just by saying that it is so, you need to provide an argument.
For example:

     Supose that a designer wants to connect some DRAM to a processor
through some sort of memory management (MMU). Let the processor provide
an address, and a signal that says that the address is ready and a memory
cycle should occur. Also, assume that the bus is a custom one, and that
the designer is free to define it.
     First, the upper part of the address from the processor is passed
through the MMU. Putting only the upper part of the address through the
MMU is a common practice. Then, the address is passed to the DRAMs.
It is common practice to have the lower part of the address go to the
row address of the DRAMs, as this makes it easier to handle refresh.
Now, the designer must figure out how to select only one bank of DRAMs.
According to the spec sheets, he can either provide the RAS strobe to
just the selected bank, or he can provide the CAS strobe to just that bank.
Let's assume that the CAS strobe is used for selecting the desired bank,
and that the RAS strobe is sent to all the DRAMs.
     Now the designer wants to minimize the number of wait states needed.
The access time of the DRAMs is specified from the RAS strobe to data
ready, so the RAS strobe should occur as soon as possible. The RAS strobe
must not occur before the row address, but as the row address is stable
when the processor requests a memory cycle, this request can be used
to trigger the RAS strobe immediatly.
     With a few simple assumptions about the sort of system that is wanted,
and doing the most logical thing at each step, (except for that one decision
about the two possible ways of selecting a bank), we now have a system
that overlaps RAS-CAS delay with the MMU. We did not have to do any
thinking to achieve this, nor did we have to make bizarr assumptions about
what we wanted. Thus, overlaping RAS-CAS delay with the MMU is obvious to
one who is skilled in the design of such systems.

Q.E.D.

jnw@mcnc