Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site ucbvax.BERKELEY.EDU Path: utzoo!decvax!ucbvax!ht.ai.mit.edu!valdes From: valdes@ht.ai.mit.edu (Raul Valdes-Perez) Newsgroups: mod.ai Subject: schematics drafting request Message-ID: <8608191641.AA21811@ht.ai.mit.edu> Date: Tue, 19-Aug-86 12:41:39 EDT Article-I.D.: ht.8608191641.AA21811 Posted: Tue Aug 19 12:41:39 1986 Date-Received: Sat, 27-Sep-86 03:59:43 EDT Sender: usenet@ucbvax.BERKELEY.EDU Organization: The ARPA Internet Lines: 21 Approved: ailist@sri-stripe.arpa I have designed and programmed a non-rule-based KBES that drafts the schematic of a digital circuit (actually only the placement part). To have an objective measure of the ability of this program, I would like to compare its output with that of any other (perhaps algorithmic) schematics drafter. I expect that a large CAD circuit design package would have something like this. Can anyone help me obtain access to such a drafter? (Please note that this has little to do with a schematic *entry* program, nor with a VLSI *layout* program. Thanks in advance. Raul E. Valdes-Perez or (valdes@mit-htvax.arpa) MIT AI Lab, Room 833 545 Technology Square Cambridge, MA 02139