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From: kjm@ut-ngp.UUCP
Newsgroups: net.arch
Subject: Re: Delayed Loads
Message-ID: <4015@ut-ngp.UUCP>
Date: Fri, 19-Sep-86 18:58:06 EDT
Article-I.D.: ut-ngp.4015
Posted: Fri Sep 19 18:58:06 1986
Date-Received: Sat, 20-Sep-86 02:40:58 EDT
References: <5100133@ccvaxa> <486@weitek.UUCP> <694@mips.UUCP> <86@mtxinu.UUCP>
Organization: UTexas Computation Center, Austin, Texas
Lines: 27

[]
> One example of this type of optimization
>that I remember was when copying two X registers (the machine's
>accumulators, more or less; they're 60-bit registers) into two
>other registers.  The obvious sequence is
>
>        BX1     X2+X2   bitwise "or" of X2 with X2 into X1
>        BX3     X4+X4   likewise for X4 into X3
>
>Redundant operatorands could be elided, so that the X2+X2 could be
>abbreviated by just using X2.
>
>[Ed Gould]

Just as a point of information, "BX1 X2+X2" and "BX1 X2", are not the
same instruction -- they generate different opcodes.  They do have the
same effect, though.

--
The above viewpoints are mine.  They are unrelated to
those of anyone else, including my cat and my employer.

Kenneth J. Montgomery  "Shredder-of-hapless-smurfs"
[Charter?] Member, Heathen and Atheist SCUM Alliance, "Heathen" division

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