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From: kim@amdahl.UUCP (Kim DeVaughn)
Newsgroups: net.arch
Subject: Re: Delayed Loads
Message-ID: <3767@amdahl.UUCP>
Date: Tue, 23-Sep-86 20:48:04 EDT
Article-I.D.: amdahl.3767
Posted: Tue Sep 23 20:48:04 1986
Date-Received: Tue, 23-Sep-86 22:48:09 EDT
References: <5100133@ccvaxa> <1115@masscomp.UUCP> <697@mips.UUCP>
Organization: Amdahl Corporation,  Sunnyvale, CA 94086
Lines: 36

[ "Send lawyers, guns, and money ..." ]

In article <697@mips.UUCP>, mash@mips.UUCP (John Mashey) writes:
>A pleasant thing about doing an architecture from scratch is the ability to
>forbid the use of stores into the instruction stream. [Obviously, you must
>be able to create executable code, but you can require a system call to
>indicate weird cache manipulations.]  There appears to be a fair amount of
>hardware in many high-end machines dedicated to worrying about this
>[relatively rare] event, which is too bad.  Had it been forbidden from
>day one, I suspect little performance would be lost; certainly, most
>high-level languages don't do this kind of thing anyway.

There is a related problem here with machines that have seperate
instruction and data caches, and which run s/w that doesn't distinguish
between "code" and "data" in the object/load file formats.

With large cache line sizes (64 byte lines on Amdahl 5890's), you can
frequently end up with data in the I-cache because the compiler gens
short chunks of code followed by short chunks of data followed by more
code, etc.  This also happens with some styles of coding in assembly
language.  So we end up "shuffling" cache-lines back and forth between
the I-cache and Op-caches.  And yes, you're right ... it does take alot
of h/w to do this kind of thing without incurring a (big) performance
penelty.

/kim


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